The present invention generally relates to data transfer control systems, and more particularly to a data transfer control system for controlling a data transfer which involves a rearrangement of data.
When making a data transfer between two regions such as when transferring data from an 8-bit input/output interface to a 16-bit memory device, it is necessary to rearrange the data.
Conventionally, as methods of making the rearrangement of data, there is a first method which employs a swap buffer and a second method which employs a temporary register. According to the first method, first 8 bits of data from an input/output interface is transferred to upper 8 bits of a 16-bit memory device, and next 8 bits of data is transferred to lower 8 bits of the memory device through a swap buffer. On the other hand, according to the second method, 8 bits of data from the input/output interface is transferred to upper 8 bits of a 16-bit temporary register, and next 8 bits of data are transferred to lower 8 bits of the temporary register. Then, the 16-bits of data from the temporary register is transferred to the 16-bit memory device.
The second method employing the temporary register requires two cycles which are a source cycle in which the data is transferred from the input/output interface (a source) to the temporary register and a destination cycle in which the data is transferred from the temporary register to the memory device (a destination). When the temporary register is employed, there is an advantage in that a start address can be set independently at the source and the destination thereby enabling a flexible rearrangement of the data.
However, in recent microcomputer systems, a bus width is extended to 32 bits, for example, and there is a need to transfer 32 bits of data. When making a data transfer between 32-bit source and the destination memories by use of a 32-bit bus, it is possible to set four kinds of start addresses at both the source and destination memories by using lower 2 bits of the address. In other words, start addresses "00", "01", "10" and "11" can be set by the lower 2 bits of the address.
For this reason, according to the second method which employs the temporary register and makes the rearrangement of the data in either one of the source and destination cycles, there are sixteen possible combinations of the start addresses because there are four possible kinds of start addresses at both the source and destination memories. As a result, sixteen kinds of control information must be provided with respect to the temporary register for making the rearrangement of the data, and there is a problem in that a control of the data transfer becomes complex.